With Nangate Library Creator, designers can control and alter the individual attributes of all digital library cells, make precise adjustments to cell parameters and to fulfill the strictest design requirements.

For example, transistor sizing strategy and row height can be set to control the trade-off between power usage, frequency and area. Drive strength variants, which can be any arbitrary number, can be set at will and the user can balance DFM trade-offs between recommended and minimum rules, thus regulating area and library yield to the desired level.

Nangate Library Creator contains the full set of tools needed to create and characterize cell libraries. It complements existing design flows and provides all of the outputs required by the physical synthesis tool chain.

Key Features and Benefits

• Intelligent library planner allowing fast and easy design space exploration with minimal data entry, which enables users to define and create the optimal library for the application in a minimum of time
• Fast setup and assimilation of process technologies and foundry design rules, down to 22nm, enabling DRC clean layout generation in the first week of use
• Scalable parallel processing, so that performance increases with the number of computing nodes and parallel simulations
• Built-in Spice simulator with optional integration with third-party Spice simulators and extraction engines
• Extensive integration with third-party DFM, DRC and LVS verification tools to ensure high-quality results and minimal interruption to flow
• Footprint-compatible cell generation using GDSII or automatically generated layouts as input for creating fine-grained drive and skew variants, enabling late-stage speed and power optimization using Nangate Design Optimizer™
• Full scripting interface support provides the flexibility to integrate Nangate Library Creator into existing design flows, and perform design goal searching through iterative loops

General Specifications

• Fully automated layout topology generation using advanced optimization algorithms that minimize cell area and parasitic effects. Optimization strategies include:
• Optimal cell input sequencing
• Optimal diffusion strip layout
• Transistor netlist synthesis with built-in transistor sizing algorithms and override options including logical effort
• Adaptive or user-enforced application of recommended rules and wire-spreading for DFM improvement
• User-definable topology generators with support for an advanced parameterized set of layout primitives:
• Contact and contact arrays
• Single and folded transistor configurations
• Advanced proprietary compaction engine:
• Adaptive topology-driven compaction strategies
• Full design-rule support for advanced CMOS processes as well as user constraints
• Scalable parallel execution of Spice simulations and layout generation through:
• LSF^TM from Platform Computing®
• SUN® Grid Engine (SGE)
• Multi- and single-threaded processing
• Built-in verification, including:
• Formal verification of layout vs. expression
• Extensive timing and power model validation
• Interface to external physical verification for independent QA
• DFM analysis and scoring through external verification tools

Cell Types

• Buffers (inverting, non-inverting, clock)
• Boolean combinational (AND, OR, NAND, NOR, AOI, OAI, OA, AO, MUX)
• Arithmetic (XOR, full-adder, half-adder)
• Sequential (latches, clock-gaters, D-type flip/flops with any optional combination of scan input, set and reset)
• Miscellaneous (tie cells, filler cells, antenna, diode, ECO gates)
• User-defined complex gates based on Boolean equations
• User-defined cells from Spice netlists

Platform Support

• Redhat Linux® x86 and x86_64

Inputs

• Foundry-provided transistor models
• Nangate Technology Language file containing foundry design rules

Outputs

• Liberty (.lib) formatted libraries with CCS timing, ECSM timing and NLDM/NLPM data
• Verilog® and Spice netlists
• VITAL and Edif formats
• Library databook in HTML and PDF formats
• Cell schematics
• GDSII (Graphics Design System II) cell layouts
• LEF (Library Exchange Format)
• Virtuoso OpenAccess database

If you would like to receive more information about the Nangate Library Creator, please register yourself at the Nangate Resource Center or send an email to .