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Nangate Design Optimizer™ is the re-synthesis solution for next-generation physical design flows. The Design Optimizer brings together standard-cell library creation with gate-level optimization to provide significant improvements in design speed, power consumption and area.

Nangate Design OptimizerRTL synthesis and physical design flows from leading suppliers all rely on a predefined, fixed standard-cell library. Standard-cell libraries are created with the intent of general-purpose usage across various design types, so compromises have to be made that affect performance on a particular design. Nangate Design Optimizer (NDO) removes these restrictions and introduces concurrent optimization of library and design.

NDO takes as input a gate-level netlist, standard-cell library and design constraints. Critical-path analysis is performed, followed by optimization based on augmenting the cell library with new design-specific cells with locally optimized timing properties.

Speed, Power and Area Optimization

When optimizing for power (static and dynamic) or area, NDO first analyzes and identifies the optimal Boolean equations suited to the cell library and the primary design goal. It then augments the library with design-specific complex cell functions that represent the optimal set of Boolean functions for the design, followed by gate-level remapping. Area and power gains of 10-30% are typically realized, depending on the design's ratio of combinational to sequential logic cells. When timing is the goal, speed gains of 10-20% can typically be achieved. Following the speed, power and area optimizations, NDO outputs an optimized gate-level netlist and an augmented library containing enhanced cells.

The Optimum Cell Mix Improves Design Performance

  • Nangate Design Optimizer creates the optimized mapped netlist based on your design goals: speed, power and area
  • NDO allows users to identify and specify key metrics of an optimal combination of standard cells for any given design, which ensures that library development teams can produce the optimal library for the specific design
  • Complements existing physical synthesis flows from Cadence, Magma, Mentor and Synopsys by providing an additional post-synthesis optimization stage that eliminates the constraints inherent in non-optimal standard-cell libraries
Design Optimizer Flow

Library Enhancement Using Logic Cell Variants

  • NDO uses existing cell libraries as input, including libraries obtained from foundries and third-party vendors
  • NDO identifies the most heavily used cells in a design and optimizes them to achieve the desired performance goal
  • Nangate patented optimization techniques perform gate-level re-synthesis using design-specific subsets of the cell library to raise a design's performance ceiling
  • Using a Nangate MegaLibrary™, NDO can access a huge selection of library and cell variants containing complex logic functions. Fabless semiconductor companies can use this approach for rapid, off-the-shelf deployment.
  • Identifies logic cell variants (drive strengths, skew factors, P/N ratios), which can be targeted for detailed analysis and enhancement
  • For customers with specific cell requirements, NDO interacts dynamically with the Nangate Library Creator™ to build the optimal library for a given design. Foundries, IDMs and IP development teams can benefit from on-the-fly cell creation to produce application-specific libraries.

Complete Integration with Other Tools

  • Seamless integration with existing third-party physical synthesis flows, implemented through application-specific interfaces
  • Nangate solutions complement RTL synthesis, STA and place & route tools from Cadence, Magma, Mentor and Synopsys
  • Straight-forward library manipulation, output and reporting via standard command set to reduce configuration overhead while maintaining full configurability

Inputs

  • Liberty™ library model files including NLDM, CCS and ECSM extensions
  • Gate-level Verilog®, DEF file
  • SDC Design Constraints
  • SPEF or SPF parasitic (optional)
  • Place & Route information

Outputs

  • Gate-level Verilog®
  • Cell specification for Nangate Library Creator
  • Enhanced libraries including GDSII, Liberty and Spice views

Platform Support

  • Redhat Linux® x86 and x86_64

If you would like to receive more information about the Nangate Design Optimizer, please register yourself at the Nangate Resource Center or send an email to .

 

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