Nangate Design Audit™ analyzes, compares and validates Static Timing Analysis results against Spice simulations of any design's critical paths or uses customer-specified paths and thereby greatly improves the accuracy and time spent in timing closure.
The Design Audit checks timing STA results by automatically extracting the n-most critical paths on any gate-level design following a Spice simulation on these to finally compare the timing results against the STA report. With Nangate Design Audit, designers can measure and control library guard-banding, qualifying or evaluating correlation between CCS, ECSM and NLDM models.
Key Features and Benefits
Utilizes customer-specific gate-level netlist, pre or post layout, as input to ensure that the correlation analysis is based on the way that the standard cells were used in the design
Provides support for static test circuit structures, allowing detailed library qualification by library groups before release to design teams
Automatically extracts the n-most critical paths or uses customer-specified paths from the design to determine the true slack with Spice accuracy
Supports all leading timing models including NLDM, CCS and ECSM to provide flexibility between most popular backend design flows
Allows easy configuration through intuitive graphical wizard of delay, slew and path limits to reduce the configuration overhead but still maintaining full configurability for advanced and scripted usage
Provides gate or net delays and/or slew into or out of cells, all provided in gate-by-gate or path-by-path comparison tables
Integrated support for closed loop with Nangate Library CharacterizerTM, thereby enabling correlation and calibration of standard-cell libraries with STA
Spreadsheets containing a library level view of deviations across all paths in the design/test structure
The use of products such as Nangate Design Audit is especially critical when:
Foundries provide updated transistor models
Introducing new tools or versions of library-driven tools into flow
Qualifying or evaluating a different timing model (NLDM vs CCS or ECSM)
Running at non-nominal PVT corners where standard cells can become significantly nonlinear in their behavior
Easy Setup with Straight-Forward GUI
Graphical User Interface (GUI) for easy setup and report viewing
Correlation of Any Path
Allows configuration of specified paths or automatic detection of critical paths
Complete Integration
Supports market-leading Static Timing Analysis engines as well as Spice circuit simulators to ensure that the analysis matches the flow
Tightly integrated with Nangate Library Characterizer, thereby enabling closed-loop correlation and validation
Platform Support
Redhat Linux® x86 and x86_64
Inputs
LibertyTM library model files including NLDM, CCS and ECSM extensions
Foundry-provided transistor models
Extracted cell Spice netlists
Gate-level Verilog® or Nangate-provided static test structures
SDC Design Constraints
SPEF or SPF parasitic (optional)
Outputs
Instant correlation and validation reports
CSV and XML formatted output with data formatted for import to other tools
HTML databook linking STA results with library characterization data
MS Excel data showing deviations from all paths for each cell of your library
If you would like to receive more information about Nangate Design Audit, please register yourself at the Nangate Resource Center or send an email to
.
Liberty is a registered trademark of Synopsys Inc.
- Making Simple Things Simple and Complex Things Possible
Products 
