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Nangate Design Optimizer™ is the re-synthesis solution for next-generation physical design flows. The Design Optimizer brings together standard-cell library creation with gate-level optimization to provide significant improvements in design speed, area and power consumption.
RTL Synthesis and Physical Design flows from leading suppliers all rely on a predefined, fixed standard-cell library. Standard-cell libraries are created with the intent of general-purpose usage across various design types, so compromises have to be made that affect performance on a particular design. The Design Optimizer removes these restrictions and introduces concurrent optimization of design and library.
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Press Releases & News |
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May 29, 2008: Free 45nm Open Source Digital Cell Library from Nangate Released in its Second Edition |
Nangate updates 45nm Open Cell Library to include CCS and ECSM current source models as well as Mentor Graphics DFM Kit
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March 3, 2008: Nangate and Si2 Release Unprecedented Free 45nm Open Source Digital Cell Library |
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Nangate donates 45nm cell library to the Silicon Integration Initiative (Si2) for improved innovation in state-of-the-art nanometer flows and methodologies
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February 18, 2008: NXP Semiconductors selects Nangate Library Creator to boost 32nm research |
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Integrated digital cell library creation and characterization solution from Nangate now deployed for advanced cell library design space explorations at NXP Semiconductor Research
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Upcoming and Past Events |
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September 2008: CDNLive! 2008 |
Nangate will exhibit at CDNLive! Silicon Valley 2008, September 9-11, 2008 at the San Jose Marriott and San Jose McEnery Convention Center, San Jose, CA.
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January 2009: EDS Fair 2009 |
The Electronic Design and Solutions Fair will take place again in 2009 in the Pacifico Yokohama, Kanagawa, Japan. The event occurs from Thursday-Friday, January 22-23, 2009.
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