• On-Silicon Testbench to Validate Soft Logic Cell Libraries
    4 Apr, 2008
    This work proposes a validation methodology to siliconprove a set of logic cells generated by software. It also presents an approach for the automatic design of testbenches to validate the cells in the set.
  • Speed-up of ASICs Derived from FPGAs by Transistor Network Synthesis Including Reordering
    15 Jan, 2008
    This paper presents a method for speeding up ASICs by transistor reordering. The proposed method can be applied to a variety of logic styles and transistor topologies. The rationale of the obtained gains is explained through logical effort concepts. When applied to circuits based on 4-input networks, which is the case of many structured ASIC or FPGA technologies, significant performance gains are obtained at a small area expense. This observation points out that our method can be of special interest when migrating FPGAs to ASICs. The logical effort effects on networks derived from BDDs illustrated in this paper can be exploited in a much broader range of designs.
  • DAG Based Library-Free Technology Mapping
    2 May, 2007
    This paper reviews the modeling of subthreshold leakage current and proposes an improved model for general series-parallel CMOS networks. The presence of on-switches in off-networks, ignored by previous works, is considered in static current analysis.
  • Modeling and Estimating Leakage Current in Series- Parallel CMOS Networks
    2 May, 2007
    This paper reviews the modeling of subthreshold leakage current and proposes an improved model for general series-parallel CMOS networks. The presence of on-switches in off-networks, ignored by previous works, is considered in static current analysis.
  • New CMOS Logic Style Based on the Minimum Theoretical Number of Transistor in Series
    15 Jun, 2006
    The propagation delay in CMOS gates is strongly related to the number of stacked PMOS and NMOS devices in the pull-up and pull-down networks, respectively. The standard CMOS logic style is usually optimized targeting one logic plane, presenting the complemented topology in the other one. As a consequence, the minimum number of transistors in series is not necessarily achieved.
  • Fast Disjoint Transistor Networks from BDDs
    15 Mar, 2006
    In this paper, we describe different ways to derive transistor networks from BDDs. The use of disjoint pull-up (composed of PMOS transistors) and pull-down (composed of NMOS transistors) planes allows simplifications that result in shorter pull-up and pull-down transistor stacks.