NanGate Design Audit™ is a versatile data analysis and validation framework that greatly improves team productivity in timing closure and library validation. It enables design and characterization teams to verify the accuracy of timing models as well as consistency across library views.


Design Audit enables library characterization that enables design teams to check timing accuracy through a SPICE Vs Static Timing Analysis (STA) analysis. It checks timing and noise STA results by automatically extracting the n-most critical paths on any gate-level design. It compares SPICE simulation of these critical paths against their STA results.


Timing constraints for library sequential cells such as setup and hold time are also validated through SPICE simulation. The Design Audit flags optimistic and pessimistic timing constraints and provides valuable data to assess design margins and quality of the library characterization process. It alerts the user when the constraint values do not guarantee safe operation independent of guard-banding.


Finally, Design Audit performs library cross-checks to inspect library views (GDSII, LEF, Spice, Liberty, Verilog, and Vital) and reports consistency issues. This is a fundamental step to avoid library error detection late in the design process.


With NanGate Design Audit, design and characterization teams can measure and control library consistency and guard-banding. It is a key tool in qualification and evaluation of CCS, ECSM and NLDM models.



Key Features and Benefits


Spice vs. STA utilizes customer-specific (pre or post layout) gate-level netlists as input to ensure that the correlation analysis is based on the way the standard cells were used in the design. It provides support for static test circuit structures, allowing detailed library qualification by library groups before delivery to design teams. Design Audit automatically extracts the n-most critical paths or uses customer-specified paths from the design to determine the true slack with SPICE accuracy.


• Cross-checks and detects library consistency issues in early development stages

• Validation of timing constraints ensures the accuracy of timing models and provides useful insights concerning design margins
• Supports all leading timing models including  NLDM, CCS and ECSM to provide flexibility  between most popular backend design flows
• Allows easy configuration through an intuitive  wizard yet still maintains full scripted usage
• Integrates support with NanGate Library Char-acterizer™ and NanGate Library Creator™ thereby enabling correlation and calibration of standard-cell libraries
• Produces spreadsheets containing a library level view of deviations across views, timing constraints and critical paths


When to use NanGate Design Audit


The use of NanGate Design Audit is especially critical when:

• Releasing a new library or library updates
• Foundries provide updated transistor models
• Introducing new tools or versions of library-driven tools into flow
• Qualifying or evaluating a different timing model (NLDM vs. CCS or ECSM)
• Running at non-nominal PVT corners where  standard cells can become significantly nonlinear in their behavior



Constraint Validation

• Design Audit validates timing constraints (setup, hold, recovery, removal and minimum pulse width) through SPICE simulation against Liberty data.

• Constraints that are pessimistic (under optimal value) or optimistic (unsafe operation leading to potential failures) are flagged in comprehensive HTML, MS Excel and TVS/ CSV reports.

• Design teams can measure and control guard-banding requirements

• The Design Audit timing constraint validation goes beyond what a user would get with simple Liberty vs. Liberty comparisons



Easy Setup with Straight-Forward GUI

• The Graphical User Interface (GUI) provides easy  setup and report viewing, yet still allowing full scripted usage  Correlation of Any Path


Correlation of Any Path

• Allows configuration of specified paths or automatic detection of critical paths



Complete Integration

• Supports market-leading Static Timing Analysis engines as well as SPICE circuit simulators to ensure that the analysis matches the design flow

• Tightly integrated with NanGate Library Characterizer/Creator




• Liberty™ library model files including NLDM, CCS and ECSM extensions
• Foundry-provided transistor models
• Extracted cell SPICE netlists
• Gate Level Verilog® or NanGate-provided static structures
• SDC Design Constraints
• SPEF parasitic (optional)
• Verilog/LEF/GDSII/VITAL (optional)





• Instant correlation and validation reports
• HTML data book linking STA results and validation of timing constraints with library characterization data
• TVS/CSV output for easy imports to other tools
• MS Excel data showing deviations for both Spice vs. STA and timing constraints validations.


Platform Support

• Redhat Linux® x86 and x86_64